The present invention relates to high efficiency low frequency amplifiers, commonly referred to as class-D amplifiers, and, more particularly, though not exclusively, to class-D audio amplifiers.
The efforts of manufacturers for reducing energy consumption, weight and size of heat sinks of consumer apparatuses, such as in the field of car entertainment, have generated a demand for power amplifiers with a greater efficiency than the traditional class-AB amplifiers.
Class-D amplifiers have been proposed to respond to these requirements. These amplifiers include a DC to AC converter circuit, which produces a PWM output signal. This PWM output signal drives output power devices through a passive lowpass filter for reconstructing an amplified analog (audio) signal. For example, the reconstructed amplified analog (audio) signal drives a load, such as a speaker, that may be a part of the lowpass filter.
The analysis of the behavior of a single ended amplifier with an analog input and a PWM output, i.e, a class-D amplifier, is described in the paper titled xe2x80x9cAnalysis Of A Quality. Class-D Amplifierxe2x80x9d by Himmelstoss et al., I.E.E.E. Transactions on Consumer Electronics, Vol. 42, No. 3, August 1996. However, the increasing interest in digital audio signal processing will make the use of digital amplifiers more convenient than analog amplifiers.
Presently, there are no known commercial applications of digital input amplifiers, and few articles describe possible design approaches. One such article is titled xe2x80x9cNoise Shaping And Pulse-Width Modulation For All-Digital Audio Power Amplifiersxe2x80x9d by Goldberg et al., Journal Audio Eng. Doc., Vol. 39, No. 6, June 1991. The described system does not use a feedback circuit on the final stage, which to some extent penalizes the performance in terms of distortion and noise rejection. The performance appears to be strictly dependent on the characteristics of the components of the power stage (FIG. 8).
Another article titled xe2x80x9cAll Digital Power Amplifier Based On Pulse Width Modulationxe2x80x9d by Pedersen et al., was presented during the 96th Audio Engineering Society (AES) convention, Feb. 26-Mar. 1, 1994, in Amsterdam. According to this design approach there is no feedback circuit. The system appears to be burdened by resorting to a linearized PWM signal.
Yet another article titled xe2x80x9cA Sigma-Delta Power Amplifier For Digital Input Signalsxe2x80x9d by Klugbauer-Heilmeier was presented during the 102nd AES convention Mar. 22-25, 1997, in Munich. This article describes a pulse density modulation (PDM) amplifier requiring a high switching frequency in addition to an anti-aliasing filter in the feedback path.
An object of the present invention is to provide a digital input PWM power amplifier functioning at a relatively low switching frequency to achieve a high efficiency.
Another object of the invention is that the PWM power amplifier is easy to make, and has a low sensitivity with respect to the spread of the actual parameter values of the circuit""s components.
Yet another object of the invention is that the PWM amplifier operates at the. lowest possible driving frequency of the PCM/PWM converter without requiring. integrated lowpass filters. The only filter of the system is a lowpass filter connected in cascade to the PWM amplifier output, which is always present in switching output stages.
These objects and others are attained by a PWM power amplifier comprising an oversampling and noise shaping circuit receiving pulse code modulation (PCM) input digital data organized in words composed of a certain number (M) of bits, and outputting PCM digital data converted into words composed of a number (N) of bits lower than the number of bits of the input data (M greater than N) at a multiple bit rate (Fin*k) equal to the bit rate (Fin) of the input data.
A first bus transmits a first fraction (P) of most significant bits (MSB) of the words output from the oversampling and noise shaping circuit, and a second bus transmits the remaining (S) least significant bits (LSB) of the words output from the oversampling and noise shaping circuit.
The first and second PCM/PWM converters respectively receive data transmitted on the first and second buses. Each converter comprises a counter that is reset by the transitions of the digital value of data fed to the respective converter. The converter functions in an up/down mode and is fed with at least a clock signal (Fclock) whose frequency is equal to the multiplied bit rate (Fin*k) of the data transmitted on the respective buses of the converter. This data is multiplied by the base 2 raised to the relative number of bits (P or S) of the transmitted words.
Each converter generates reference digital words composed by the respective number of bits (P or S) representing incremental and decremental digital values. These values define single or multiple slope rising and descending ramps of digital values whose rate is identical to the bit rate of the data fed to the converter. A digital comparator receives through a first input the reference digital words generated by the up-down counter, and receives through a second input the input data, and outputs a PWM digital signal (MSBdig, LSBdig) at a switching frequency equal to the bit rate of the input digital data stream.
The PWM output signal (MSBdig) of the first converter that receives the fraction (P) of most significant bits is summed on the inverting input node (xe2x88x92) of a final power amplifying stage of the amplifier to the PWM output signal (LSBdig) of the second converter (LSBdig). This signal is attenuated by a ratio equivalent to the base 2 raised to the number (S) of bits transmitted through the second bus to the input of the second converter.
The pair of PCM/PWM converters may be of the single or multiple ramp type. The use of double ramp converters, i.e., with a succession of rising and falling ramps, enhances the amplifier performance in terms of distortion and of the signal-to-noise ratio as compared to a single ramp converter. The reference signal for a double ramp converter is substantially a triangular waveform. The reference signal for a single ramp converter is substantially a saw-tooth waveform.
The output signal produced by the single final power stage in the case of a single ended amplifier or of the two final power stages in the case of a bridge configuration, i.e., upstream of the lowpass analog signal reconstructing filter(s), is a PWM signal whose frequency is equal to the output signal (MSBdig) produced by the first converter but has a different duty-cycle as a function of the following parameters: supply voltage of the final power stage; nonlinearity and losses of the final power stage; and correction made to the signal (LSBdig) output by the second converter.